TSMC Chief: Our 3nm Node Will Beat Intel 18A

When Pat Gelsinger returned to Intel as CEO in 2021, he established a "five nodes in four years" IDM 2.0 strategy designed to return the company to dominance by 2025. The thinking was that it would out-engineer its rival TSMC by working on numerous next-generation nodes in parallel and then transitioning to them rapidly. This would allow it to leapfrog TSMC by 2025, at which point it would be back on top of the industry it ruled for decades. It is/was a solid plan, and it might just work, but now TSMC's chairman has weighed in on it for the first time, essentially dismissing Intel's plans as a pipe dream.

TSMC Chairman C.C. Wei was asked about Intel's long-term strategy on a recent earnings call, and the typically diplomatic executive did not hold back at all. The call was transcribed by Fool.com, and flagged by Wccftech. He was asked if TSMC will lose technology leadership to Intel when Chipzilla hits the end of its IDM 2.0 strategy at the Intel 18A process. At this point, Intel is expected to use backside power delivery, 3D "Foveros" chip stacking, ribbonFET transistors, and sub 2nm technology as 18A is theoretically 1.8nm. C.C. bluntly said not only will it not lose to Intel, but its 3nm process will be able to beat Intel at sub-2nm for several reasons.

Intel is expected to end its "five nodes in four years" journey in 2025 or so. Credit: Intel

Mr. Wei began his comments by stating that he does not underestimate Intel at all, nor does he take Intel lightly. He noted that TSMC's internal analysis has shown that its N3P process is comparable with Intel's 18A node in power, performance, and density/size despite the size difference (3nm versus 1.8nm, theoretically). At the same time, he noted that TSMC will maintain technological superiority despite Intel offering backside power delivery at 18A due to its N3P node being earlier to market, more mature, and at a lower cost.

Essentially, he argues that the company's tried-and-true FinFET N3 design will be more reliable than Intel's cutting-edge ribbonFET technology, as fewer new technologies will be involved that can cause problems and reduce yields. Plus, N3P is the company's third generation design, following N3 and N3E, which is aimed at boosting performance through increased logic density, and it's slated for a 2024 arrival. This is right around when Intel is expected to unveil the final stage of its IDM 2.0 strategy, which is its 18A technology. This is due in 2024 to 2025, when TSMC is expected to begin to transition from 3nm to its own 2nm nanosheet GAA transistors as well.

There's a little more than 2 years left on this clock/strategy, and 3 nodes left to unveil. Credit: Intel

Overall, it's a mildly shocking display of confidence in the face of Intel's engineering onslaught. Mr. Wei makes no bones that he thinks TSMC will continue to dunk on its biggest rival, even when its IDM 2.0 strategy reaches its climax in two years. We'll have to wait and see if he was right or if Gelsinger will have the last laugh. It's at this stage of the game where timely execution is critical. Delays led TSMC to snatch the title from Intel in the first place back when it couldn't move past 14nm.